The invention relates to a method and a device for controlling the thickness of a layer of an integrated circuit in real time during an engraving process.
When manufacturing integrated circuits, it may be desirable to measure the thickness of a layer of this integrated circuit deposited during the preceding steps of implementing this manufacturing process.
This is particularly the case when manufacturing memory cells of the EPROM type, where the technology used requires an insulating stack to be provided between two conductive layers, known as a control gate and a floating gate respectively.
The stack produced, more commonly known as ONO, which stands for Oxide, Nitride, Oxide, is made up of a layer of silicon oxide, SiO2, a layer of silicon nitride, Si3N4, and a second layer of silicon oxide, this stack being sandwiched between the floating electrode and the gate electrode. This structure as a whole, deposited on a silicon substrate of the P type for example, is isolated by a layer of silicon oxide as illustrated by the diagrams of FIG. 1a and 1b giving a view across the width and the length respectively of the channel.
The structure and the stack thus formed constitute part of the core of the EPROM memory cell and can be programmed in particular by injecting electric charges into the first conductive layer or floating gate, the programming state being memorised by maintaining the injected charge over time.
The thickness of the second layer of silicon oxide disposed between the layer of silicon nitride Si3N4 and the control gate may vary between 20 and 50 Angstroms, 1 xc3x85=10xe2x88x9210 m, depending on the technologies used. This layer may be formed by conventional thermal oxidation or by a deposition technique of one type or another.
However, it is crucial to control the quality and thickness of this second layer of oxide since these factors primarily contribute to ensuring that the memory cell produced does not age, ageing implying the loss of electric charges after programming. For a more detailed description of the correlation between the phenomenon of ageing in this type of EPROM memory cell and the silicon thickness, reference may be made to the articles entitled:
Threshold Voltage Instability and Charge Retention in Non-volatile Memory Cell with Nitride/Oxide/Nitride double-layered Inter-poly Dielectric, published by Seiichi Mori et al. 1991/IEEE/IRPS;
Bottom-ox scaling for thin Nitride/oxide interpoly dielectric, published by Seiichi Mori et al. IEEE Transactions on Electronic Devices, Vol.39, No 2, February 1992 ;
Thickness Scaling Limitation Factors of ONO Interpoly Dielectrics, Seiichi Mori et al. IEEE Transactions on Electronic Devices, Vol.43, No 12, January 1996.
At present, when running the processes to manufacture EPROM memory cells, the controls which have to be carried out on this thickness are generally delayed, being carried out on a separate silicon sample using an appropriate measuring apparatus, i.e. not as part of the manufacturing process applied to the production plates. Accordingly, apart from incurring a loss of the time needed to take a delayed measurement, the above-mentioned measuring technique poses a major problem in terms of reliability because the kinetics of oxidation on silicon and on silicon nitride can be very different. Consequently, for a same thickness of silicon oxide formed on a silicon sample, the corresponding silicon oxide may vary by a factor of 1 to ⅓ on the production plate. Furthermore, producing this layer of silicon oxide requires the use of high-performance measuring equipment in order to take a measurement of this layer on this sample.
The objective of this invention is to remedy the above-mentioned drawbacks of the prior art by eliminating the use of a sample silicon oxide deposition and by operating a method of measuring the thickness of a layer of an integrated circuit in real time during the production process, in particular when engraving this integrated circuit.
The method of measuring the thickness of a layer of an integrated circuit in real time, which will be referred to as the thickness to be measured, deposited on an underlying layer, is performed during an operation whereby the substrate of this integrated circuit incorporating these layers is engraved.
It is remarkable in that it consists in tracking the forward movement of the engraving front of each layer of the integrated circuit by plotting the optical emission spectrum of the product of the engraving reaction in real time on at least one spectral component of the underlying layer, establishing a distribution of the amplitude of the optical emission of the engraving reaction product as a function of time and determining the transition of the optical emission on this distribution as the engraving front passes from the layer to be measured to the underlying layer. The thickness of the layer to be measured is calculated on the basis of this distribution and the transition by means of a correlation to this transition on this distribution.
The method proposed by the invention may be applied to measuring the thickness of integrated circuit layers deposited on an underlying layer of any type but is more particularly suited to measuring the thickness of the second silicon oxide layer deposited on an underlying layer of silicon nitride, such as used to produce EPROM cells on an industrial scale.